Microprocessor designers are increasingly relying on greater amounts of cache memory in order to increase their performance. In addition, new manufacturing processes, for example, 65 and 45 nanometer (nm) processes are enabling hardware designers to incorporate more cache memory in their designs. Cache memory is extremely fast memory used by the central processing unit to reduce the average time to retrieve data from the most frequently accessed primary memory locations.
Higher density manufacturing processes (e.g., 65 and 45 nm) are resulting in greater current leakage. These manufacturing processes are enabling microprocessor designers to incorporate increasing amounts of cache memory in their designs. Therefore, both the increasing quantity of cache memory and the higher density of microprocessor designs are both contributing to an increase in current leakage, even when the microprocessor is not in use.
Typically, static random access memory (SRAM) is implemented as cache memory on board the microprocessor. Data from an SRAM memory cell is read by first precharging the entire SRAM array and then evaluating the data from the appropriate memory cell. An example of a cache memory element circuit is a two port eight transistor SRAM (8T SRAM). An 8T SRAM is comprised of a memory storage circuit and two separate ports, one for reading data from the memory storage circuit and one for writing data to the memory storage circuit. Data is stored in the memory storage circuit which is comprised of two N channel field effect transistors (NFETs) and two P channel field effect transistors (PFETs). In conventional operation, data is written to the memory cell via a write word line (WWL) and a write bit line (WBL), each coupled to a NFET which is in turn coupled to the memory storage circuit.
Data is read from the memory circuit via an NFET read stack, which is comprised of two NFETs connected in series, with one end coupled to a read bit line and the other end coupled to ground. The gate of the NFET coupled to the read bit line is coupled to a control signal, and the gate of the NFET coupled to ground is coupled to the memory storage circuit.
A read operation is executed by first precharging the read bit line during the first phase of the clock cycle. During the second phase of the clock cycle the data stored in the memory circuit is evaluated via the activated read bit line. If the value read from the memory circuit equals 0 then the read bit line is discharged, and if the value read from the memory circuit equals 1 then the read bit line remains charged (i.e. from the precharge). Note that in the prior art, the steady state of all local and global bit lines of a SRAM array containing this type of memory cell is precharged.
A problem associated with this memory cell is that after an SRAM cell is precharged, current leakage occurs in the NFET read stack. In some designs a majority of the microprocessor's power consumption during an active mode is lost to leakage in arrays of SRAM cache memory cell. For idle microprocessors, SRAM memory array leakage can account for as much as 50% of overall power consumption. Current leakage is an increasing concern to both microprocessor designers and users, given the increased number of SRAM memory cells incorporated in microprocessor designs and the increasing use of powerful microprocessors in both portable devices and large server farms. Another major concern is that increased power consumption is also contributing to greater amounts of heat being generated by microprocessors.
Traditional methods employed to conserve power in microprocessors include employing power reducing modes such as shutdown and hibernate modes. Both these modes conserve power when the microprocessor is not in use. In shutdown mode memory and microprocessor states are first stored to secondary memory (e.g., a hard disk). Power to the microprocessor is then shut off. Prior to using the microprocessor, memory and states need to be restored from secondary memory when power is reapplied. In hibernate mode (also referred to as sleep mode) voltage to the microprocessor is reduced to a minimum level, which is sufficient to retain data and states stored in the microprocessor, but is not sufficient to enable operation of the microprocessor.
While both shutdown and hibernate modes save power, they only save power when the microprocessor is not in active mode (also called functional mode). During active mode, the current leakage issue still persists. Furthermore, there is a performance penalty exacted when entering and exiting these power saving modes. This is especially true in shutdown mode where a large amount of data to be is transferred to and from secondary storage when entering and exiting this mode.
Therefore, there is a need for a mechanism to reduce current leakage in SRAM arrays while the microprocessor is in both active and inactive modes. Reducing current leakage during both active and inactive modes should result in power savings without impacting memory array performance.